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Potentiometer multisim

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ELEC 161 Electronics II

Module 6 Lab: Other Integrated Circuits - Generation of Clock signals

Introduction.- In this laboratory exercise, we will work with other Integrated Circuits and will focus on the generation of clock signals that can be used to drive some analog and digital circuits.

Procedure

1. The 555 Timer as an Astable Multivibrator

The 555 Timer is located in the Mixed Mixed_Virtual Library of Multisim as shown in Figure 6-1.

Figure 6- 1: Location of the 555 Timer in Multisim

ELEC 161 – Module 6 Laboratory - Page 2

1.1 Build the Astable Multivibrator shown in Figure 6.2

Figure 6- 2: Astable Multivibrator

1.2 Calculate the theoretical oscillation frequency for this circuit.

1.3 Run the simulation. Connect the Oscilloscope at the output of the circuit and measure the frequency of the output signal. Don’t forget to include screenshots.

1.4 Compare the results from 2.2 and 2.3

1.5 Measure the duty cycle for the signal (The duty cycle is defined as the time the signal is high divided by the total period of the signal. This value will always be lower than 1. A duty cycle of 0.5 or 50% means that the signal is symmetrical).

1.6 Modify the circuit so the frequency of the new signal is approximately equal to 15 kHz. Include screenshots with the measurement of the new frequency.

ELEC 161 – Module 6 Laboratory - Page 3

2. Schmitt Trigger Oscillator

A similar circuit based on the same principle, is the Schmitt_Trigger oscillator shown in Figure 6-3. The Schmitt Trigger is a comparator with hysteresis, meaning that the threshold for going to high to low is different to the threshold from going to low to high.

Figure 6- 3: Schmitt Trigger Oscillator

This device is available in the Misc_Digital group of Multisim as shown in Figure 6-4

Figure 6- 4: Location of the Schmitt Trigger

ELEC 161 – Module 6 Laboratory - Page 4

2.1 Build the circuit shown in Figure 6-3. You may ask yourself what is the purpose of the 12 V DC source and the 10 kΩ resistor. These two components do not do anything other than “trick” Multisim. In order to perform the simulations we are doing, Multisim needs a Voltage or Current source.

2.2 Connect the oscilloscope at the output of the circuit. Verify that the circuit is oscillating. Include screenshots.

2.3 Connect a potentiometer in place of the resistor as shown in Figure 6-5.

Figure 6- 5: Oscillator with Potentiometer

Potentiometers are located in the “Basic” family of components as shown in Figure 6-6.

ELEC 161 – Module 6 Laboratory - Page 5

Figure 6- 6: Location of Potentiometers in Multisim

In order to fine tune the potentiometer, we must change its increment from the default value of 5% to 1%. To do this, double click on the potentiometer and activate bthe “Value” tab as shown in Figure 6-7.

Figure 6- 7: Parameters for potentiometers

ELEC 161 – Module 6 Laboratory - Page 6

2.4 Vary the value of the potentiometer from 0% to 100% visualizing the output signal on the oscilloscope. Record the frequency of the signal for at least 15 different values of resistance.

2.5 Using Excel or similar software create a plot that shows frequency of the signal (Y-axis) versus resistance (X- axis).

3.- Ring Oscillator

The ring oscillator shown in Figure 6-8 is a “quick and dirty” method to generate a clock signal. It is based on an odd number of digital inverters. Although its frequency is not very stable, it can work in applications that do not require a very stable frequency.

3.1 Build the circuit shown in Figure 6-8. Once again, the voltage source and resistor are only used because of Multisim requirements. If you built your circuit using real components, those would not be necessary. In this case, pay attention that different families of digital circuits have different behaviors. Also, note that the point that interconnects the 2 resistors and the capacitor is not ground.

Figure 6- 8: Basic Ring oscillator

We have created the inverters using NAND Gates. These are available in the “Misc_Digital” family of Multisim as shown in Figure 6-9.

ELEC 161 – Module 6 Laboratory - Page 7

Figure 6- 9: Location of NAND gates

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