FPGA implementations of machine learning system

                    In 21st century, the beginning show that a huge emergence that are related to phenomenon of big data.  To the unprecedented volumes of unstructured data led by the ubiquity of devices that are capable of consuming and generating information. In this regard, for the automatic extraction of useful knowledge and pattern from the data, science field such as Data science aim to provide methods. The emerging field of deep learning has been led by the forefront of data science. By means of a sequence of trainable features extractions stages in order to facilitate the pattern recognition task at hand then the data learning give focus on using the large amount of available data to learn a hierarchy of intermediate representations. Computing powder has been one of the primary driving forces behind the success of Deep learning, apart from the abundance of available data. The building of adequate infrastructure of computing constitutes a major challenge that typical deep learning models being computationally complex in both the training and classification phase. For building the high performance deep learning system, one candidate platform is FPGAs. The deep learning system based on FPGA have huge potential that offer tradeoff tunable with in critical system parameters like performance, cost and power consumption that serve in the wide range of settings, as a useful component along the racks of the data center from an IP in Low power embedded systems to an accelerator. There are many issues arises that enhance the complexity and technicality of the deep learning system development related to FPGAs. There is a need for tools that abstract the hardware resources details of a specific platform FSGA based and scalability and guarantee portability with the FPGAs size and resource specifications changing at a fast pace. With different characteristics a deep learning model implementation can be modified to operate on FPGA platform secured by the portability. In case of an increase in the amount of available resources, scalability would ensure the ability to sustain or improve the performance. By means of domain specific modeling framework, this task give more attention on the design space exploration for the basic task of the deep learning model of convolutional neural network capture on to reconfigurable FPGA based platforms. While complying with the platform specific resources restriction, the proposed methodology wants to provide the infrastructure and the analytical tools that would allow a deep learning expert to achieve the implementation of hardware of a convent onto a target FPGA based platform. In the deep learning literature several variations of convent architecture have been proposed. There are three main type of layers going to used as sequence layer are poling layer, nonlinear layer and convolutional layer. These layer s aim to get useful features from the input information. Furthermore, different set of kernels are used to explore the several features of map are going to produced.so there are many techniques and methodologies that are very much helpful in operating the machine systems.  (stylianos I.Venieris, 2016)

Introduction of FPGA implementations of machine learning system

                The deep convolutional neural networks obtain excellent performance for many computer vision segments that include semantic segmentation, object detection and image classification. At the cost of major computational complexity as it needed a comprehensive assessment across the feature maps of all the regions where the significant accuracy improvement of CNNs comes. Hardware accelerators such as GPU, FPGA and ASIC have been employed to accelerate CNN towards such overwhelming computation pressure. Due to its high performance, energy efficiency and reprogarmability the FGPA have emerged as a promising solution among the accelerator. High level synthesis using C++ and C has greatly lowered the programming hurdle of FPGAs and improve the productivity which is consider as more important. Multiple layers are involved in the CNN typically where the output feature maps of one layer treated of the following layer the input features maps. CNN are dominated by the convolutional layers shown by the computation. Each element in the output features map is computed individually by using multiple multiply accumulated operations by using the conventional convolution algorithm. Greater efficiency is possible when the algorithm itself can be more efficient while the prior FPGA solutions of CNN using this algorithm have demonstrated preliminary success. A tile of elements in the output features map are generated together by exploiting the structural similarly among them by using winograd algorithm. By reducing the required number of multiplication, this help to cut down the arithmetic complexity. With small filters, the fast winograd algorithm can be used to drive efficient algorithms for CNNs. The most important thing is that the trend of current time period for the CNN is belong to deeper topologies with filters of small size. For efficient implementation of CNNs, this provide the opportunity of using the winograd algorithm. Several problems remain although using the winograd algorithm on FGPAs is appealing. The first problem is to match the memory throughput with the computation engines with the design can not only minimize the memory bandwidth requirements. The second problem is when mapping the winograd algorithm onto FGPA there exist a large design space. It is also important to determine which design harm the performance or which one is improve the performance. A line buffer structure designs are cache for feature maps for the winograd algorithm, it gives the permission for different tiles to again use the data during the progress of convolution operations. The winograd algorithm computations involve element wise multiplications and a mixed matrix transformation of general purpose matrix multiplication. FPGAs are obtaining the fame for the use as accelerators for the deep learning tasks because of high performance with reconfigurability and low power. Their main focus on the convolutional layer implementation using the conventional algorithm. Further the design space exploration technique also used to maximize the throughput for the computation resources and aspects bandwidth. Dynamic precision data also proposed for quantization to increase the efficacy DSP.a uniform implementation for convolutional layer and FC layer also targeted by many studies.  (liqiang Lu, 2017)

Literature review of FPGA implementations of machine learning system

            Of a deep network, RBM s have been used to train efficiently for each layer. With one input layer, one classified layer and several hidden layers are used in composing the DNN. Layer adjacent in unit are weighted connected all to all. By means of a sequence of trainable features extractions stages in order to facilitate the pattern recognition task at hand then the data learning give focus on using the large amount of available data to learn a hierarchy of intermediate representations. Computing powder has been one of the primary driving forces behind the success of Deep learning, apart from the abundance of available data. From given input neurons to the output neurons with the current network configuration, the prediction process contains the feedforward computation. Between the units in adjacent layers and global training which globally tune the connection weights with the back propagation process with the training process include pertaining which locally tune the connection weights. Consequently, is poses a significant challenge to FGPA implementation compared with the GPU and CPU optimization measures that use considerable memory bandwidth and computing resources are needed to support the parallel processing. High level synthesis using C++ and C has greatly lowered the programming hurdle of FPGAs and improve the productivity which is considered as more important. Multiple layers are involved in the CNN typically where the output feature maps of one layer treated of the following layer the input features maps. CNN are dominated by the convolution layers shown by the computation. For processing the tiled subset of data each designed hardware accelerator is able to buffer. The accelerator architecture is reused for order to support the large scale neural networks. To the computation of the hardware accelerator the access of data for each tiled subset can be run in parallel. The output neurons are reused as the input neurons in the next iteration for each iteration. We need to multiply the input neuros by each column in the weights matrix, we generate the output neuros for each iteration. 

            For the deep learning application ranging from the classification of image or video, recognition and analysis to natural language understanding, CNN is the one of the key algorithm for advance in medicine and more. Convolution operation on the multiple dimensional arrays as summarized as core computation in algorithm. For massive parallelization and extensive data reuse it also offers significant potential. Due to the customizability of FPGAs, of CNN seen an increased amount of interest from academia. FPGA main focus on the design of CNN with the on chip computation engine optimization by parallel strategies for different exploiting. (Xuechao wei, 2017)

            With the kernel of weights that have been learned in the training phase have each input features map is convolved, several features map are produced a t the convolutional layers by applying the set of different kernels. By applying an activation function in a pre-pixel basis the nonlinear operates in this regard as typical activation functions are sigmoid. For replacing the value of a feature map at a particular location with a summary static around a predefined neighborhood and in this way achieving spatial invariance and for this polling layer is responsible. On an adaption of the roofline model and explores the tradeoff between communication and computation to perform the hardware implementation optimization for the proposed methods. The synchronous data flow is considering as the basic framework. It is a special data flow case and constitutes a widespread model for both software and hardware parallel computation. A s a directed graph name SDF graph a computing system is also presented. Where the arcs indicated the data stream and nodes represent the computations. The basic principle of using this SDF is whenever the data is available in its input arcs, the nodes are fires and lead to concurrency of data driven model. (chao wand, 2017)

Conclusion of FPGA implementations of machine learning system

            To accelerate CNN-based applications, the FPGAs have been widely used. By the computational capability on the FPGA the prior implementation based on the conventional convolutional algorithm are normally limited. Based on the winograd algorithm, this work proposes a CNN architecture on FPGA that can be effectively reduce the arithmetic complexity.to estimate the resources usage and performance, also develop analytical model.   We also presented the DLAU that is flexible and scalable based on FGPA on the deep learning accelerator. It consists of three processing units of pipeline that can be used again and again for the neural network of large scale. To partition the input node data into smaller sets and compute rapidly by time sharing the arithmetic logic so the DLAU use tile techniques in this regard. So basically the main usage of machine system is to deliver the information from input to output and perform functions in most effective manner but the main issue is that the information transfer path way is very complicated and can be distributed into small and large scale according to requirement of the machine. Different models and techniques are going to used according to different designs of the machine and according to their mechanism that give best results and also handle all the issues that are belong to past problems of the machine. 

Reference of FPGA implementations of machine learning system

chao wand, l. g. (2017). A sclable deep learning accelerator unit on FPGA. 513-517.

liqiang Lu, y. l. (2017). evaluating the fast algorithms for convolutional neural networks on FPGAs. 101-108.

stylianos I.Venieris, c.-s. b. (2016). a framwork for mapping convolutional neural netorks on FPGAs. 40-47.

Xuechao wei, c. h. (2017). automated systolic array architecture synthesis for high throughput CNN inference on FPGAs.