Multiplexer & Demultiplexer

Theory of Operation & design of Multiplexer & Demultiplexer

To construct the multiplexer it’s important to understand the mechanism of the each component. Here in the first figure we draw the 8*1 MUX with the following inputs and Y as a output as well as the selection key. Based on the combination of the selection key the output is finalized in the truth table. Now, we have to implement the 8*1 MUX with the help of two 4*1 MUX, thus for 8 inputs we required 2 4*1 Mux, on each of the Muxes with two selection line S₁ & S₂ as shown the figure above. As there are three selection lines in the 8*1 MUX named as S₂, S₁, S₀, one additional selection line is also required. But the question is that where this additional line is added. As in the 4*1 there is two selection lines only let’s look on the truth table 2. We take S₂ as the enabled for two 4*1 MUX, from first four output S₂=0 along with from last four inputs the enabled key S₂=1. At the end we acquire with the result. We have applied the not gate and at the onetime only one 4*1 mux operate or activate. Here we discuss the MUX now its time to discuss the Demux. Demux is just the inverse of mux. In the below we draw the figure one is with enable function and the other is without enabling [1].

Along with the truth table & implementation is shown below;

Code of Multiplexer & Demultiplexer

Test bench of Multiplexer & Demultiplexer

Waveform of Mux of Multiplexer & Demultiplexer

VHDL code for Demux of Multiplexer & Demultiplexer

Reference of Multiplexer & Demultiplexer