8-bit wide 8-to-1 multiplexer and 1-to-8 demultiplexer using the 4-to-1 multiplexer and 1-to-4 demultiplexer in VDHL

Introduction of 8-bit wide 8-to-1 multiplexer and 1-to-8 demultiplexer using the 4-to-1 multiplexer and 1-to-4 demultiplexer in VDHL

For my second project,my main objective is to Design,Implement,and Test an 8-bit wide 8-to-1 multiplexer(Mux) and an 8 bit wide 1-to-8 demultiplexer(Demux). Similar to my first project, i built my 2-To-1 Mux, 4-To-1 Mux,1-to-2 Demux and 1-to-4 Demux in advance,following the law of combinational logic design, and used them in my final objective coding construction.In order to accomplish my goal, VHDL, which is VHSIC very high-speed hardware description language, is introduced to be my tool.

Theory of Operation and Design Explanation:

Multiplexer

Figure 1: Basic Multiplexer Work Theory and Symbol

The multiplexer(Mux) is a device that selects one of several  input signals and forwards the selected input into a single line. For a multiplexer, which has 2ⁿ inputs, it needs n select lines in order to function well. In short, a multiplexer switch one of input lines through to a single common output line by the application of a control signal.

Demultiplexer of 8-bit wide 8-to-1 multiplexer and 1-to-8 demultiplexer using the 4-to-1 multiplexer and 1-to-4 demultiplexer in VDHL

The demultiplexer(Demux) is a device that  take one data input and a number of selection inputs, and they have several outputs. They forward the data input to one of the outputs .depending on the values of the selection inputs.The demultiplexer converts a serial data signal at the input to a parallel data at its output lines as shown below.(Figure 2)

Figure 2: Basic Demultiplexer Symbol

Eight Bit Two-to-One Mux of 8-bit wide 8-to-1 multiplexer and 1-to-8 demultiplexer using the 4-to-1 multiplexer and 1-to-4 demultiplexer in VDHLto-4 demultiplexer in VDHL

Figure 3: Truth Table and Logic Circuit of A Two-To-One Mux

Following Figure 3, i built my two-to-one Mux using two inputs,which is A and B in my codes, one select line(Sel) and declared one Output. Notice that our final goal should be eight bit wide. So I made A,B and Output vectors, whose length is eight(7 down to 0). The Boolean function for a two-to-one Mux is Output = (notSel).A + Sel.B

What i expected in my two-to-one Mux is when the select line is low, it can assign the value of A to the Output. Else, when the select line is high, the value of B is assigned to the Output. In order to accomplish that, i used process in my architecture of codes. By implementing basic ‘if’ logic, I think i get it work properly, which will also be tested in next session.

Below is my codes of two-to-one Mux:(Figure 4).

Figure 4:Two-to-One Mux Code in VHDL

Eight Bit Four-To-One Mux 

Figure 5:Truth Table and Logic Circuit of A Four-To-One Mux

Following the truth table and logic circuit of a four-to-one Mux, i need to declare four inputs(A,B,C,D) and One output(Output) in my design. This time, the number of inputs is 4, which equals to 2². Therefore, two select lines are introduced to be involved in my design.(Figure 6)

Figure 6:Multiplexer Input Line Selection of 8-bit wide 8-to-1 multiplexer and 1-to-8 demultiplexer using the 4-to-1 multiplexer and 1-to-4 demultiplexer in VDHL

Based on the truth table, if i declare my select to be a vector(Sel) as 1 down to 0, there are four different situations in this case. When both of the select lines are low, the value of A will be assigned to the output. When Sel(1) is low and Sel(0) is high, the value of B will be assigned to the output. When Sel(1) is high and Sel(0) is low, the value of C will be assigned to the output. When both of the select lines are high, D will be given to the output.Below is my VHDL code for the four-to-one mux.(Figure 7)

Figure 9:Eight Bit Eight-To-One Mux Code In VHDL

Eight Bit One-to-Two Demux

Back to the demux part, the eight bit one-to-two demux functions the reverse way to the eight bit two-to-one mux.

Figure 10:Logic Diagram for an One-to-Two Demux

So in this case, when the select line is low, the value of input will be given to Y1. When the select line is high, the value of input will be given to Y0.Below is my VHDL code for my eight bit one-to-two Demux.(Figure 11)

Figure 11:One-to-Two Demux Code in VHDL

Eight Bit One-to-Four Demux

Similar to the eight bit four-to-one mux, two select lines are needed in this case as well.Shown in Figure 12

Figure 12:Demultiplexer Output Line Selection

Figure 13: Logic diagram for One-to-Four Demux

Figure 14:Truth Table for One-to-Four Demux

Based on Figure 13&14, i decided to use one inputs and four outputs in my design. Because of that the number of select lines are two, there are four situations in this case.

 When both of the select lines are low, the value of input will be given to A.When the first select line is low and the second is high, the value of input will be given to B. When the first select line is high and the second is low, the value of input will be given to C. When both of them are high, the value of input will be given to D.Below is my code for eight bit One-to-Four Demux:(Figure 15)