Report on Final Projects of the DRAM and SRAM design by using the LTSpice

Abstract of the DRAM and SRAM design by using the LTSpice

The lab report is about the DRAM and SRAM design by using the LTSpice. The design of the SRAM consists of the 2×2SRAM memory circuits and the bit line is powered by the 6V voltage source, and bit is stored for 3ns. The design of the DRAM consist of the 4×4  DRAM memory circuits and the bit line is powered by the 6V voltage source, and bit is stored for 1ns and bit line read for 2ns and bit line write for 1ns.

Keywords: DRAM, SRAM,

Introduction of the DRAM and SRAM design by using the LTSpice

Random Access Memory (RAM) is a hardware device where the data related to Operating system, applications are kept so that the access to the processor is fast. RAM is the main memory in a computer and is much faster with other kind of storage found in computers like HDD, SSD or flash storage. RAM is a volatile memory which means the data is there as long as the computer is on and all the data is lost whenever the computer is turned off. We can think of ram as a set of boxes which can either hold a 0 value or a 1 value. The box is termed as a called and a set of these boxes is called an array. Address bus is used to address a specific where the address of the row and the specific column is needed [1].

There are two main types of RAM which are called Dynamic Random Access Memory or DRAM and Static Random Access Memory or SRAM. The DRAM is the type of RAM which is used as the main memory in computer. In DRAM each cell stores charge (representing the 1 value) or the lack of charge (representing 0 values) in an electrical capacitor. As electrical capacitor can discharge on their own, the data must be refreshed constantly with an electronic charge. A transistor determines if the value of a capacitor can be read or written. In SRAM a transistor is used to save the bit as 1 or 0. To store one bit of data SRAM needs multiple transistors which means the size of SRAM is much bigger compared to DRAM but with higher speed compared to SRAM. Due to this, DRAM is not used as the main memory but L1 and L2 cache [2].

Background of the DRAM and SRAM design by using the LTSpice

In 1T1C DRAM, there is one transistor and one capacitor per memory cell. Transistor is turned on when a voltage is applied to the gate of NMOS. The source node of NMOS will change the capacitor; the capacitor retains this charge for a limited period of time which is called Retention Time. Word line voltage is given to activate transistor and the transistor is OFF when there is no voltage [3]. The charge in the capacitor starts to dissipate due to the dielectric used in capacitor which results in the data loss in DRAM. This is one of the major drawbacks in DRAM. This is overcome with the use of refresh signal which refreshed the charge in the capacitor after certain amount of time so that data is not lost. 

In an SRAM a memory usually has six MOSFETS and 4 transistors store a bit in SRAM. The transistor here M1, M2, M3 and M4 form two cross-coupled inverters. The storage cell has two states which represent 0 and 1. There are two other transistors which control the access of the storage cell in case of a read or a write operation. There are other configurations of a memory cell of an SRAM as well but this configuration is the most widely used one.

Material

In this lab report for the design of the 2×2 SRAM and 4×4 DRAM the material which is used is given below;

Two pull up Circuit

Row decoder

Column decoder

Sense amplifier

Transistor switch

Capacitors

MOSFETs

Methodology of the DRAM and SRAM design by using the LTSpice

In this lab report there are two phases of design. In the first phases of design the memory cell is powered through the two various lines of the voltage sources. Whereas the word line runs either by the row or column and the Bit line

runs by the perpendicular. And in the second phases the circuit which built work with the RAM and also operate through the detection of low power signal with the bit line and amplify those to recognizable by logic levels of the output.  In this lab report there are two types of sense amplifier is used,

Differential amplifier (operates for voltage)

Non-Differential amplifier (operates for current)  [4]

Result of the DRAM and SRAM design by using the LTSpice

The below schematic circuit for the various circuit component like the column decoder, sense amplifier, row decoder , write circuit and the read circuit which is also design to build the complete SRAM cell as well as also test the circuit which is designed. The power which is consumer through the SRAM cell array (2×2) in the writing 1 and also found the 3.53mw that is also in the writing 0 found to be 2.964mw [5]. In the 2×2 SRAM cell array, there are 4SRAM cells, two pull up circuit, column decoder, row decoder and the sense amplifier along with 2 write circuit which are used in below circuit;

Figure: 2×2 SRAM cell array

SRAM use the transistors in the flip-flop which is cross coupled and the configuration does not have the issue of leakage and it also does not refresh, and it does not used the capacitors ;

Figure: RAM cell with six transistors

By writing the charge to a capacitor through the method of access transistors the DRAM stores the data. DRAM also looks at the states of transistor charge where the capacitor charged states is the 1-bit low charge;

Figure: DRAM stores one bit as memory

There are different transistor- capacitors which together and created the word of memory [6];

Figure: Array of DRAM cells forms words.

Discussion of the DRAM and SRAM design by using the LTSpice

After the analysis the study the comparison of the DRAM and SRAM is shown in the below table;

DRAM:

DRAM is found the computer memory and it not recommend for the long-term storage. The size of the DRAM is approximately 1GB, 2 GB which is commonly found in the tablets and smartphone. The capacity of the DRAM is also the 4GB to 16GB in various laptops. There is larger storage capacity in the DRAM, and the DRAM is reasonably priced. DRAM is the simplistic in the design as well as it is very easy to implement where the number of transistors is also presented in the memory modules and impacts on the capacity.

SRAM

L2 and L3 in caches units in the CPU are the general areas of the SRAM applications. The storage capacity of the SRAM is 1MB to the 16MB. Usually SRAM in smaller size and is very expensive as compare to the DRAM. Design and construction of the SRAM is very complicated which is also used in the various kinds of transistors for their performances [7].

Conclusion of the DRAM and SRAM design by using the LTSpice

Summing up all the discussion it is concluded that the lab report is about the design of the DRAM and SRAM. In this lab report the DRAM design is based on the  4×4 and the

The “bit” must be read for 2ns and “bit” must be stored for 1ns and “bit” must be written in 1ns. And in the circuit of the SRAM design is based on the  4×4 and the 6V voltage source is provided and bit stored for 3ns. All the requirements and objectives are fulfilled.

References of the DRAM and SRAM design by using the LTSpice

[1] A. Ney et al , "A New Design-for-Test Technique for SRAM Core-Cell Stability Faults," Conference: Design, Automation and Test in Europe, DATE 2009, Nice, France,, 2009.

[2] N. Singla et al , "Design and Performance Evaluation of DRAM Memory Array on Different Technologies," International Journal of Science and Research (IJSR), 2015.

[3] R. K. Sah et al , "Performance Comparison for Different Configurations of SRAM Cells," International Journal of Innovative Research in Science, Engineering and Technology, 2015.

[4] Prof. A. Mason, "Memory Basics," 2019. [Online]. Available: https://www.egr.msu.edu/classes/ece331/mason/web_files/HO8_Memory.pdf.

[5] A. Raj S.N et al , "Design and Implementation of Low-Power Cache Memory for Mission-Critical Embedded Systems," Proc. of Int. Conf. on Multimedia Processing, Communication and Info. Tech., MPCIT, 2013.

[6] . S. THORNTON , "What is DRAM (Dynamic Random Access Memory) vs SRAM?," 22 June 2017. [Online]. Available: https://www.microcontrollertips.com/dram-vs-sram/.

[7] H. A. Abdulkadhim, "IMPLEMENTATION OF STORAGE DEVICE (RAM) USING MULTISIM," Diyala Journal of Engineering Sciences, pp. 20-36, 2012.