Core i7 cache line size

Computer Architecture

Department of Electrical Engineering & Computer Science
Computer Architecture CSCI 510
NAME
DATE RANGE
Friday, October 4, 2019 –Sunday, October , 2019

INSTRUCTIONS
This comprised of 10 equally weighted questions from Chapters 1 and 2. Answer all 10 questions. Each question is worth 10 points.

Exercise 1.9

a) Assumptions (servers turned off = 45%)

b) Assumptions (servers in “barely alive” state = 45%)

c) Assumptions (voltage reduction = 33%; frequency reduction 62%)

Exercise 1.11

a) Assumptions (company computers = 8,500; MTTF for each computer = 26 days; catastrophic failure = ½ of computers failing)

b) Assumptions (extra cost of doubling MTTF per computer = $520)

Exercise 1.14

a) Assumptions (increased speedup of FPOs = 3x; FPOs = 31% of original program execution time)

b) Assumptions (speeding up the FPU resulted in 1.7x slowdown; data cache access = consumes 16% of execution time)

c) Unchanged

Exercise 1.15

a) Unchanged

b) Unchanged

c) Unchanged

d) Unchanged

e) Unchanged

Exercise 1.16

a) Assumptions (percentage of application that is parallelizable = 55%; communication cost = 0)

b) Assumptions (# of processors = 12; communication overhead per each processor added = 0.72%)

c) Assumptions (# of processors = 12; 0.72% increase in communication overhead when number of processors is doubled)

d) Assumptions (communication overhead is increased by 0.72% of the original execution time whenever the # of processors is doubled)

e) Unchanged

Chapter 2 Questions (Answer all five)

Exercise 2.17

a) Unchanged

b) Unchanged

c) Unchanged

Exercise 2.18

a) Unchanged

b) Unchanged

c) Unchanged

d) Unchanged

Exercise 2.21

a) Unchanged

b) Unchanged

c) Unchanged

Exercise 2.36

Exercise 2.40