Half adder in multisim

Instructions:

Please download this document and type in your answers for questions in parts 1 and 2; save this document using the following format: CT212Lab6firstname_lastname.doc.

Introduction

One class of combinational logic consists of decision circuits, in which the circuit evaluates the input signals to determine which specific action to take. The 2-of-3 voting logic circuit in Experiment 5 is an example of a decision circuit. Another important class of combinational logic consists of arithmetic functions, in which the circuit processes numeric (binary) data. Many of the earliest digital circuits were designed to perform highspeed calculations, and arithmetic functions today are found in a wide variety of calculating and measuring devices. The basis of arithmetic functions is a device called the adder, which, as its name suggests, adds two bits. There are two basic varieties of adders, called the half-adder and full adder.

The half-adder has two inputs, corresponding to two input bits, and two outputs, which indicate the sum and carry that result from adding the two input bits. A limitation of the half-adder is that it cannot add groups of bits, as the carry from one column cannot propagate to the next column. The full adder is similar to the halfadder but adds a third input, called the carry in. The carry in allows the full adder to accept the carry bit from a previous adder so that groups of bits can be added. Figure 6-1 shows the diagram of a half-adder and full adder.

In Part 1 of this experiment, you will examine and verify the operation of a full adder circuit. In Part 2, you will examine how a 4-bit full adder is cascaded to add 8-bit and wider numbers.

Reading

Kleitz, Digital Electronics: A Practical Approach with VHDL, 9th Edition, Chapter 5.

Multisim Files

Part 1: Digital_Exp_06_Part_01a and Digital_Exp_06_Part_01b

Part 2: Digital_Exp_06_Part_02a, Digital_Exp_06_Part_02b, and Digital_Exp_06_Part_02c

Key Objectives

Part 1: Examine, verify, and compare the gate-level implementations of the full adder.

Part 2: Examine and verify the operation of cascaded 4-bit binary adders.

Part 1: The Full-Adder

6.0 Implementation 1

1) For each row in Table 6-1, record the expected sum and carry values for the “Cin”, “A” and “B” inputs for a full adder in the “Σ” and “Cout” columns.

2) Open the Multisim file Digital_Exp_06_Part_01a .

3) Start the simulation.

4) Use the “A”, “B”, and “C” keys to open and close the “Input A”, “Input B”, and “Carry In” switches for

each of the settings shown in Table 6-2. Alternatively, you can click on the switches to open or close them.

5) Record the state of the “Sum” and “Carry Out” probes for each combination of switch settings in the “Σ” and “Cout” columns of Table 6-2.

6) Stop the simulation.

Table 6-1: Sum and Carry Outputs for Full Adder

Cin

A

B

∑

Cout

Cin

A

B

∑

Cout

0

0

0

1

0

0

0

0

1

1

0

1

0

1

0

1

1

0

0

1

1

1

1

1

Table 6-2: Observed Outputs for Full Adder Implementation 1

Cin

A

B

∑

Cout

Cin

A

B

∑

Cout

0

0

0

1

0

0

0

0

1

1

0

1

0

1

0

1

1

0

0

1

1

1

1

1

6.2 Implementation 2

1) Open the Multisim file Digital_Exp_06_Part_01b .

2) Start the simulation.

3) Use the “A”, “B”, and “C” keys to open and close the “Input A”, “Input B”, and “Carry In” switches for

each of the settings shown in Table 6-3. Alternatively, you can click on the switches to open or close them.

4) Record the state of the “Sum” and “Carry Out” probes for each combination of switch settings in the “Σ”and “Cout” columns of Table 6-3.

5) Stop the simulation.

Cin

A

B

∑

Cout

Cin

A

B

∑

Cout

0

0

0

1

0

0

0

0

1

1

0

1

0

1

0

1

1

0

0

1

1

1

1

1

Questions for Part 1

1) How could you configure a full adder to operate as a half-adder?

2) Do the outputs of the full adders in Table 6-2 and Table 6-3 match the expected values in Table 6-1?

3) What advantage, if any, does the full adder in Digital_Exp_06_Part_01b have over the full adder in