If a memory reference takes 200 nanoseconds, how long does a paged memory reference take?

Consider a paging system with the page table stored in memory.

a. If a memory reference takes 50 nanoseconds, how long does a

paged memory reference take?

b. If we add TLBs, and 75 percent of all page-table references are found

in the TLBs, what is the effective memory reference time? (Assume

that finding a page-table entry in the TLBs takes 2 nanoseconds, if

the entry is present.)

Answer:

a. 400 nanoseconds: 200 nanoseconds to access the page table and 200

nanoseconds to access the word in memory.

b. Effective access time = 0.75 × (200 nanoseconds) + 0.25 × (400

nanoseconds) = 250 nanoseconds.

Consider the following segment table:

Segment Base Length

0 219 600

1 2300 14

2 90 100

3 1327 580

4 1952 96

What are the physical addresses for the following logical addresses?

a. 0,430

b. 1,10

c. 2,500

d. 3,400

e. 4,112

Answer:

a. 219 + 430 = 649

b. 2300 + 10 = 2310

c. illegal reference, trap to operating system

d. 1327 + 400 = 1727

e. illegal reference, trap to operating system

232 bytes. The computer has 218 bytes of physical memory. The virtual

memory is implemented by paging, and the page size is 4096 bytes.

A user process generates the virtual address 11123456. Explain how

the system establishes the corresponding physical location. Distinguish

between software and hardware operations.

Answer:

The virtual address in binary form is

0001 0001 0001 0010 0011 0100 0101 0110

Since the page size is 212, the page table size is 220. Therefore the loworder

12 bits “0100 0101 0110” are used as the displacement into the page,

while the remaining 20 bits “0001 0001 0001 0010 0011” are used as the

displacement in the page table.

What is the cause of thrashing? How does the system detect thrashing?

Once it detects thrashing, what can the system do to eliminate this

problem?

Answer:

Thrashing is caused by underallocation of the minimum number of

pages required by a process, forcing it to continuously page fault. The

system can detect thrashing by evaluating the level of CPU utilization as compared to the level of multiprogramming. It can be eliminated by

reducing the level of multiprogramming.

Consider a system that allocates pages of different sizes to its processes.

What are the advantages of such a paging scheme? What modifications

to the virtual memory system provide this functionality?

Answer:

The programcould have a large code segment or use large-sized arrays

as data. These portions of the program could be allocated to larger pages,

thereby decreasing the memory overheads associated with a page table.

The virtual memory system would then have to maintain multiple free

lists of pages for the different sizes and also needs to havemore complex

code for address translation to take into account different page sizes.