Ram rom prom eprom eeprom pdf

Microcontrollers

Please scan your homework solutions and email to grader (rizard@clemson.edu) with a copy to me (jgowdy@clemson.edu). 1. For the each of the statements below, circle the memory types, from the list provided, for which the statement is true. (a) Information in this memory is not lost if the power to the chip is removed. RAM, ROM, PROM, EPROM, NON-FLASH EEPROM, FLASH EEPROM (b) After an initial set of values has been stored in this memory, it cannot ever be changed. RAM, ROM, PROM, EPROM, NON-FLASH EEPROM, FLASH EEPROM (c) This non-volatile memory can be erased and reprogrammed, but the entire contents of the memory must be erased to do this. RAM, ROM, PROM, EPROM, NON-FLASH EEPROM, FLASH EEPROM (d) A small section (one byte or possibly a small number of bytes) of this non- volatile memory can be erased and reprogrammed, without having to erase the entire chip. RAM, ROM, PROM, EPROM, NON-FLASH EEPROM, FLASH EEPROM 2. How many 1M by 1-bit memory chips would be needed to implement a memory system of size 4M by 8 bits?

2

3. (a) A memory system for computer with a 20-bit address bus is to be designed so that either one byte or two consecutive bytes (starting on an even address) can be accessed on one bus cycle. This memory is to consist of the following memory chip pairs: Memory chip pair Size of chip pair (sum of both members of pair) RAM 0 and RAM 1 128K RAM 2 and RAM 3 128K RAM 4 and RAM 5 64K RAM 6 and RAM 7 64K RAM 8 and RAM 9 128K RAM 10 and RAM 11 32K Set up the Address Table that could be used to perform the Address Table Method of address decoding for this memory system. DO NOT DETERMINE THE CRITICAL ADDRESS LINES FOR THIS PART OF THE PROBLEM. Starting A19 A18 A17 A16 A15 A14 A13 Address (in K) ____ ____ ____ ____ ____ ____ ____ RAM 0 ____ RAM 1 -------------- RAM 2 ____ RAM 3 -------------- RAM 4 ____ RAM 5 -------------- RAM 6 ____ RAM 7 ------------- RAM 8 ____ RAM 9 ------------- RAM 10 ____ RAM 11

3

(b) For another memory system design problem using the Address Table Method, the following Address Table has been set up as shown below. Perform the next step of design by placing an asterisk, *, by each "critical address line." Starting A19 A18 A17 A16 A15 A14 A13 Address (in K) ____ ____ ____ ____ ____ ____ ____ RAM 0 ___0___ 0 0 0 RAM 1 ---------- RAM 2 __128K__ 0 0 1 RAM 3 ---------- RAM 4 __256K__ 0 1 RAM 5 ---------- RAM 6 __512K__ 1 0 0 0 RAM 7 --------- RAM 8 __576K__ 1 0 0 1 RAM 9 --------- RAM 10 __640K__ 1 0 1 RAM 11

4

(c) Below is sketched a diagram for one of the chip pairs, RAM 4 and RAM 5, in the system of part b. Based on your answer to part b, show how to interface these memory chips to the Address Bus, Data Bus, and Control Bus of the computer. Assume that the Control Bus includes the following signals: MEMR* MEMW* LSTRB* (same usage as on 256B microcontroller) Assume that RAM 4 stores the even-addressed bytes and RAM 5 stores the odd-addressed bytes over the assigned address range.

RAM 4

A0-A16

CS1

CS2

D0-D7

RD WR

RAM 5

A0-A16

CS1

CS2

D0-D7

RD WR

5

4. A memory system for a computer with a 20-bit address bus is to consist of a total of 608K 8- bit locations. (Assume that only bytes--not words-- can be accessed on each read or write.) The number of bytes contained in each chip is shown below in the left-most column. Complete the address table below and determine the minimum set of critical address lines for interfacing the chips in this memory system. (Consistent with this approach, assume that no future expansion of the memory system is expected.) Starting A19 A18 A17 A16 A15 A14 Chip Addr ____ ____ ____ ____ ____ ____ Size 64K ROM 0 ________ 64K ROM 1 ________ 128K ROM 2 ________ 256K RAM 0 ________ 64K RAM 1 ________ 32K RAM 2 ________ (b) If at a later time, an additional 32K RAM is added, starting at location 608K, which, if any, of the memory chips involved in the original design would respond when software is trying to access a location assigned to the new RAM.

6

5. (a) A pair of 32K x 8-bit EPROM memory chips are used together to implement part of the memory system for a computer with an 18-bit external Address Bus. The computer has the capability of accessing either byte or word operands in memory. Given that the Address Table approach indicates that the only "critical address line" for interfacing this pair of chips is A17 = 1, what overall address range does this pair of chips cover? (b) Below is shown a block diagram of the pair of EPROM memory chips discussed in part a. Based on the information in part a, show how to interface these chips to the buses of the computer. (Show what each of the external connections in the figure below should be connected to.) Note that OE stands for "output enable." The bar over the “OE” indicates that it is a low-active signal. Assume that the control bus includes the following signals: LSTRB* (same usage as on 256B microcontroller), MEMR*, and MEMW*

OE CS1 CS2

chip 1

A0-A14 D0-D7

OE CS1 CS2

chip 2

A0-A14 D0-D7

7

(c) From the information in part a, what can we say about the overall size of the external memory system being interfaced?

8

6. Consider two different implementations of a memory system consisting of dynamic RAM memory chips. In both cases, the total memory size is 1024K by 8 bits (1M by 8 bits). The time it takes to perform a read, write, or refresh operation on the chips in both systems is the same. (Call this time T1.) The max time allowed for a complete refresh of both types of chips is also the same. (Call this time T2.) Implementation A is implemented using 256Kx1 bit memory chips Implementation B is implemented using 1M x 1 bit memory chips If 2% of the available bus time is required for performing refresh of the memory chips in System B, what would be the corresponding percentage required for refreshing the memory chips in System A? Make clear how you arrive at your answer.