4 bit asynchronous down counter using jk flip flop

The project involves using Altera Quartus® II CAD system and proceeding with the following requirements:

Design and simulation of a four-bit Up-Down counter; you will need to use Flip-Flops JK negative edge triggered 74112. The flip flops are available in .mf library. This flip flops come in Dual-Packages so all you need is two of them. Implementation with other class of devices, like 71LS161/163 will not be considered. You need to take into consideration the following: a) The simulations should use a clock of 25 MHzb) The snap shots should show a complete count (from 0000 to 1111 and another for a count from 1111 to 0000), and should show uses of Asynchronous Clear and Preset. (SEE Attached PDF for Project Counter examples)

Bonus points implementing with ALTERA boards DE2-115. (Please do this)

Each student will turn in a report with the results of their design and simulation of the circuits.(SEE Attached Project Guidelines Document for report details and all project requirements).Objective: Design and simulate a 4-bit Synchronous Up-Down Counter in Quartus II. GUIDELINES: 1. Each student will turn in a report with the results of their design and simulation of the circuits. The report should contain: • Theory of operation: Explain how your circuit works, but do not give implementation details. This should be an expanded version of the introduction. That is to give a high level description of what your circuits do and how they do it. For example, you could explain any algorithms you implemented, any conditions or restrictions the user must observe to use the circuits, and the high level structure of your circuits at the block diagram level. • Design details: This subsection is where you can go into the details of your design. It should contain any logical expressions you use, any Karnaugh maps or algebraic simplifications you performed, and any tables or state diagrams for sequential circuits. It should explain design techniques if they are not self explanatory. It should refer to the detailed documentation (such as schematic diagrams) explicitly. This section should also contain a description of any unusual problems you had and how you solved them • Schematic Diagrams. Make sure all input and output connectors are labeled with the proper signal name. Add labels for any interior signals that appear in the written description of the circuit, especially those that appear in logical expressions • The waveform resulting from the time simulation. Do as many simulations you consider that show the functionality of the circuit. You should set the waveform in the same order of variables that you provide in the truth tables. i) Use only functional simulation. • Analysis, including comments and conclusions 2. Design and simulation of a four-bit Up-Down counter; you will need to use Flip-Flops JK negative edge triggered 74112. The flip flops are available in .mf library. This flip flops come in Dual-Packages so all you need is two of them. Implementation with other class of devices, like 71LS161/163 will not be considered. You need to take into consideration the following: a) The simulations should use a clock of 25 MHz b) The snap shots should show a complete count (from 0000 to 1111 and another for a count from 1111 to 0000), and should show uses of Asynchronous Clear and Preset. Bonus points implementing with ALTERA boards DE2-115. (Please do this) Only documents submitted as Microsoft Word (.doc or .docx) or .PDF formats will be considered. Enhanced Burglar Alarm report and all Altera Quartus® II CAD system files (bdf, vwf, etc) CET 3116 Project 3 Counter Examples • The basic synchronous UP-counter shown is limited to MOD numbers that are equal to 2N. • Where N is the number of FFs. Digital Systems: Principles and Applications, 11/e Ronald J. Tocci, Neal S. Widmer, Gregory 1 CET 3116 Project 3 Counter Examples • A synchronous down counter is constructed in a similar manner to an up counter. • It uses the inverted FF outputs to control the higher-order J, K inputs. Synchronous, MOD-16, down counter and output waveforms. Digital Systems: Principles and Applications, 11/e Ronald J. Tocci, Neal S. Widmer, Gregory 2 CET 3116 Project 3 Counter Examples • In a parallel up/down counter, the control input controls the values fed to the J and K inputs of the successive FFs. • The normal FF outputs or the inverted FF outputs. Digital Systems: Principles and Applications, 11/e Ronald J. Tocci, Neal S. Widmer, Gregory 3 CET 3116 Project 3 Counter Examples 4 • For the first five clock pulses, Up/Down = 1. • The counter counts up. • For the last five pulses, • The counter counts down. Digital Systems: Principles and Applications, 11/e Ronald J. Tocci, Neal S. Widmer, Gregory Up/Down = 0. ...