Difference between latch and flip flop with timing diagram

a) (5 marks) Explain the difference between a latch, a gated latch and a flip flop. b) (5 marks) A gated SR latch has the following schematic diagram CLK a) Draw a timing diagram showing the Q and Q outputs for the following sequence of inputs: CLK R Assume that the initial state of the outputs is Q 0 and Q 1 c) (5 marks) Draw a schematic diagram for a rising edge-triggered master-slave D flip- flop built using two gated RS latches and any other necessary logic gates. Hint: the other necessary logic gates will likely be 3 inverters. d) (5 marks) The D input of a D flip flop has minimum set-up and hold time constraints with respect to its active clock edge. When connecting asynchronous signals to a D 2 of 5 flip flop these constraints will not always be met. Why is this a problem and what can be done about it? e) (5 marks) Draw a schematic diagram of a 3-bit synchronous binary counter with a synchronous reset but no enable input. The circuit should have a clock input "clk" reset input "rst", and a 3 bit output q2, q1 & q0. The counter should be positive edge-triggered and built entirely from D flip-flops and logic gates. Assume that your flip flops have a synchronous reset input.a) (5 marks) Explain the difference between a latch, a gated latch and a flip flop. b) (5 marks) A gated SR latch has the following schematic diagram CLK a) Draw a timing diagram showing the Q and Q outputs for the following sequence of inputs: CLK R Assume that the initial state of the outputs is Q 0 and Q 1 c) (5 marks) Draw a schematic diagram for a rising edge-triggered master-slave D flip- flop built using two gated RS latches and any other necessary logic gates. Hint: the other necessary logic gates will likely be 3 inverters. d) (5 marks) The D input of a D flip flop has minimum set-up and hold time constraints with respect to its active clock edge. When connecting asynchronous signals to a D 2 of 5 flip flop these constraints will not always be met. Why is this a problem and what can be done about it? e) (5 marks) Draw a schematic diagram of a 3-bit synchronous binary counter with a synchronous reset but no enable input. The circuit should have a clock input "clk" reset input "rst", and a 3 bit output q2, q1 & q0. The counter should be positive edge-triggered and built entirely from D flip-flops and logic gates. Assume that your flip flops have a synchronous reset input.